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Efficient Reed-Solomon Decoder with Adaptive Error-correcting Capability

Platform : VLSI

IEEE Projects Years : 2010

Abstract—Reed-Solomon (RS) codes are widely used as errorcorrecting codes in digital communication and storage systems. This paper proposes an efficient architecture for RS decoder with adaptive error-correcting capability. This decoder can be employed to enable complexity-performance tradeoff and ensure data reliability in applications with time-varying channel condition, such as wireless communications. Specifically, the proposed decoder adopts the low-complexity Chase (LCC) algebraic soft-decision decoding algorithm. This algorithm tests 2 vectors, and larger  leads to higher error-correcting capability. The proposed decoder is capable of implementing LCC decoding with variable . In addition, the decoder hardware units are reused to incorporate harddecision decoding (HDD). Detailed hardware requirement and latency analysis is provided for a (255, 239) RS code. Compared to the LCC decoder for  = 3 only, the adaptive RS decoder that can take care of both the HDD and LCC decoding with  2 {3, 4, 5} only has 1% area overhead. Index Terms—Adaptive error-correcting capability, Algebraic softdecision decoding, Hard-decision decoding, Low-complexity Chase, Reed- Solomon codes, VLSI design. I. INTRODUCTION Reed-Solomon (RS) codes are widely used in digital communication

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