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Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication

Platform : VLSI

IEEE Projects Years : 2009

Abstract—As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive asynchronous protocols for robust system-level communication. However, in practice, it is extremely inefficient to build local asynchronous computation nodes with two-phase logic, hence four-phase (i.e., return-to-zero) computation blocks are typically used. This paper proposes two new architecture for a family of asynchronous protocol converters that translate between two- and four-phase protocols, thus facilitating robust system design using efficient global two-phase communication and local four-phase computation. A converter circuit is implemented and evaluated a 0.18 micron TSMC process through post-layout simulation, assuming both a small computation block (8 8 combinational multiplier) and an empty computation block (FIFO stage). Index Terms—Asynchronous design, delay-insensitive encoding, digital design, global communication, on-chip networks.

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