Project Login
Registration No:


Platform : VLSI IEEE PROJECTS 2011

IEEE Projects Years : 2011


1 A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic IEEE 2011 IEEE 2011

2 A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems IEEE 2011 IEEE 2011

3 Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph IEEE 2011 IEEE 2011

4 A Read-Disturb-Free, Differential Sensing 1R/1W Port,8T Bitcell Array IEEE 2011 IEEE 2011

5 Configurable Multimode Embedded Floating-Point Units for FPGAs IEEE 2011 IEEE 2011

6 Reconfigurable Routers for Low Power and High Performance IEEE 2011 IEEE 2011

7 FPGA Based on Integration of CMOS and RRAM IEEE 2011 IEEE 2011

8 Application-Aware Topology Reconfiguration for On-Chip Networks IEEE 2011 IEEE 2011

10 A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC) IEEE 2011 IEEE 2011

11 Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface IEEE 2011 IEEE 2011

12 A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design IEEE 2011 IEEE 2011

13 Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design IEEE 2011 IEEE 2011

14 Two-Stage, Pipelined Register Renaming IEEE 2011 IEEE 2011

15 An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC IEEE 2011 IEEE 2011

16 A Novel Programmable Parallel CRC Circuit IEEE 2011 IEEE 2011

17 GALS-based LPSP: Implementation of a Novel Architecture for Low Power High Performance Security Processors IEEE 2011 IEEE 2011

18 A GALS FFT Processor with Clock Modulation for Low-EMI Applications IEEE 2011 IEEE 2011

19 A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications IEEE 2011 IEEE 2011

20 GALS Design for On-Chip Ground Bounce Suppression IEEE 2011 IEEE 2011

21 Active Memory Processor for Network-on-Chip Based Architecture IEEE 2011 IEEE 2011

22 Implementation of Time-Multiplexed Sparse Periodic FIR Filters for FRM on FPGAs IEEE 2011 IEEE 2011

23 An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM IEEE 2011 IEEE 2011

24 A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes IEEE 2011 IEEE 2011

25 High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree IEEE 2011 IEEE 2011

27 Location Cache Design and Performance Analysis for Chip Multiprocessors IEEE 2011 IEEE 2011 28 Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM IEEE 2011 IEEE 2011

29 A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor IEEE 2010 IEEE 2011

30 Implementation of a 64-point FFT on a Multi-Processor System-on-Chip IEEE 2009 IEEE 2011

31 An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM IEEE 2007 IEEE 2011

32 Standby Current Reduction of Compilable SRAM Using Sleep Transistor and Source Line Self Bia IEEE 2006 IEEE 2011

33 SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction IEEE 2005 IEEE 2011

34 Automated Placement for Parallelized FPGA FFTs IEEE 2011

35 High-Throughput, Lossless Data Compression on FPGAs IEEE 2011

36 Automatic HDL-based generation of homogeneous hard macros for FPGAs IEEE 2011

37 Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-Core Processors IEEE 2011

38 Design of a FPGA-Based Parallel Architecture for BLAST Algorithm with Multi-hits Detection IEEE 2011

39 FPGA Based High Performance and Scalable Block LU Decomposition Architecture IEEE 2011

40 A novel design methodology for implementing reliability-aware systems on SRAM-based FPGAs IEEE 2011

41 A High Performance and Memory Efficient LU Decomposer on FPGAs IEEE 2011

42 FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters IEEE 2011

43 Parallel FPGA-based Implementation of Recursive Sorting Algorithms IEEE 2011 44 Skein Tree Hashing on FPGA IEEE 2011

45 Reconfigurable Cache implemented on an FPGA IEEE 2011

46 Evaluation of white-box and grey-box Noekeon implementations in FPGA IEEE 2011

47 Evaluation of white-box and grey-box Noekeon implementations in FPGA IEEE 2011

48 VLSI Implementation of Balanced Binary Tree Decomposition based 2048-point FFT/IFFT Processor for Mobile WI-Max IEEE 2011

49 Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing IEEE 2011

50 Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes IEEE 2011

51 VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm IEEE 2011

52 VLSI Architecture of Arithmetic Coder Used in SPIHT K IEEE 2011

53 Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA IEEE 2011

54 Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic IEEE 2011

55 Pipelined Parallel FFT Architectures via Folding Transformation IEEE 2011

56 Loop Acceleration Exploration for ASIP Architecture IEEE 2011

57 A Low-Power Low-Cost Design of Primary Synchronization Signal Detection IEEE 2011

58 Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials IEEE 2011

59 Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT IEEE 2011

60 High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm IEEE 2011

61 Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches IEEE 2011

62 Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis IEEE 2011 63 Efficient Pattern Matching Algorithm for Memory Architecture IEEE 2011

64 Multiple curve presentation and zooming processor using Field Programmable Gate Arrays IEEE 2011

65 Design and Implementation of Area-optimized AES Based on FPGA IEEE 2011

66 Multiple curve presentation and zooming processor using Field Programmable Gate Arrays IEEE 2011

67 Joint Optimization of Run-Length Coding, Huffman Coding, and Quantization Table With Complete Baseline JPEG Decoder Compatibility_sim IEEE 2009

68 A Fully Pipelined Architecture for the LOCO-I Compression Algorithm for images_Sim IEEE 2009

69 A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet IEEE 2009 70 A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise in images_Sim IEEE 2009

71 A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time IEEE 2009

72 A Multibank Memory-Based VLSI Architecture of DVB IEEE 2009

73 A Parallel Pruned Bit-Reversal Interleaver IEEE 2009

74 Adaptive Frequency-Domain Channel Estimator in 4X4 MIMO-OFDM Modems IEEE 2009

75 Adaptive IIR Filtering of Noncircular Complex Signals IEEE 2009

76 An Efficient 4-D 8PSK TCM Decoder Architecture IEEE 2009

77 Asynchronous Current Mode Serial Communication IEEE 2009

78 Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication IEEE 2009

79 CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects IEEE 2009

80 Design and Implementation of a Field Programmable CRC Circuit Architecture IEEE 2009

81 Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique IEEE 2009

82 Design of Voltage Over scaled Low-Power Trellis Decoders in Presence of Process Variations IEEE 2009

83 Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation IEEE 2009

84 Energy-Efficient Sub threshold Processor Design IEEE 2009

85 Fast Scaling in the Residue Number System IEEE 2009

86 Integrated Solar Energy Harvesting and Storage IEEE 2009

87 Multi-Gbps LDPC Code Design and Implementation IEEE 2009

88 Noisy FIR identification as a quadratic eigenvalue problem IEEE 2009

89 Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension IEEE 2009

90 On the Relay Channel With Receiver–Transmitter Feedback IEEE 2009

91 Optimized Analog flat filter design IEEE 2009

92 Scalable Multi-Input–Multi-Output Queues With Application to Variation-Tolerant Architectures IEEE 2009

93 Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters IEEE 2009

94 Spectrally Shaped Generalized MC-DS-CDMA with Dual Band Combining for Increased Diversity IEEE 2008

95 Single Chip Encryptor Decryptor Core Implementation of AES Algorithm IEEE 2008

96 Serial Search Code Acquisition Using Smart Antennas with Single Correlator or Matched Filter IEEE 2008

97 Practical Asynchronous Interconnect Network Design IEEE 2008

98 Fast Elliptic Curve Cryptography on FPGA IEEE 2008

99 A Novel Approach to Design BCD Adder and Carry Skip BCD Adder IEEE 2008

100 A Novel Carry-look ahead approach to an Unified BCD and Binary Adder_Subtractor IEEE 2008

101 Injecting Intermittent Faults for the Dependability Validation of Commercial Microcontrollers IEEE 2008

102 Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation IEEE 2008







CALL: 08985129129 ,  E-Mail Id: