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4-BIT ADDER CUM SUBTRACTOR

Platform : vlsi

IEEE Projects Years : 1988

AIM: IMPLEMENTATION OF 4-BIT ADDER CUM SUBTRACTOR IN VDHL ABSTRACT The design of a 4×4-bit multiplier using the modified Booth's algorithm in 2-μm NMOS technology is discussed. The main features of this chip are its 62.5-MHz operating frequency and 31.5-mW power dissipation. The chip occupies an area of 1.37 mm2. A novel adder-cum-subtractor circuit was designed to realize the arithmetic processing part. LEARNING OBJECTIVE: To understand about 4-Bit Adder Cum Subtractor in VHDL INPUT: Data / information about 4-Bit Adder Cum Subtractor OUTPUT : Simulated output of 4-Bit Adder Cum Subtractor in VHDL APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

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