Project Login
Registration No:
Password:
MAIL ALERTS SMS ALERTS
 
     
   
     

4-BIT CARRYLOOK AHEAD ADDER

Platform : vlsi

IEEE Projects Years : 1993

AIM: IMPLEMENTATION OF 4-BIT CARRYLOOK AHEAD ADDER IN VHDL ABSTRACT A high-speed adder scheme based on transistor sharing in multiple output static CMOS complex gates having recursive relations among output expressions (called recursive output property) is introduced. A brief transistor sharing technique for extracting the subfunction from the given Boolean function implemented with a static CMOS complex gate is described, and the technique applied to the design of a 32 bit CLA (carry look-ahead adder). Simulation using HSPICE with 1.5 mu m CMOS model parameters for the case of a 32 bit carry look-ahead adder has shown a reduction of the total number of transistors in the 4 bit carry look-ahead circuit from 56 of the conventional scheme down to the 32 of the authors' proposed scheme with a speed improvement of approximately 12.5% for 32 bit addition. LEARNING OBJECTIVE: To understand about 4-Bit Carrylook Ahead Adder in VHDL INPUT: Data / information about 4-Bit Carrylook Ahead Adder OUTPUT : Simulated output of 4-Bit Carrylook Ahead Adder APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

NOW GET PROJECTS ! GET TRAINED ! GET PLACED !

IEEE, NON-IEEE, REAL TIME LIVE ACADEMIC PROJECTS,

PROJECTS WITH COMPLETE COURSES,SOFT SKILLS & PLACEMENTS

ALLOVER INDIA & WORLD WIDE,

HOSTEL FACILITY AVAILABLE FOR GIRLS & BOYS SEPARATELY,

CALL: 08985129129 ,  E-Mail Id: support@ascentit.in

REGISTER FOR PROJECTS NOW ! GET DISCOUNT
   
1