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4-BIT COMPARATOR

Platform : vlsi

IEEE Projects Years : 1997

AIM: IMPLEMENTATION OF 4-BIT COMPARATOR IN VHDL ABSTRACT Using ramp-type Josephson junctions a 4-bit periodic threshold ADC has been designed, fabricated and tested. Practical design constraints will be discussed in terms of noise immunity, flux flow, available technology, switching speed etc. In a period of four years we fabricated about 100 chips in order to bring the technology to an acceptable level and to test various designs and circuit layouts. This resulted in a basic comparator that is rather insensitive to the stray field generated by the analog input signal or variations in mask alignment during fabrication. The input signal is fed into the comparators using a resistive divider network. Full functionality at low frequencies has been demonstrated LEARNING OBJECTIVE: To understand about 4-Bit Comparator in VHDL INPUT: Data / information about 4-Bit Comparator OUTPUT : Simulated output of 4-Bit Comparator in VHDL APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

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