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2:4 DECODER

Platform : vlsi

IEEE Projects Years : 2005

AIM: IMPLEMENTATION OF 2:4 DECODER IN VHDL ABSTRACT Various log-likelihood-ratio-based belief-propagation (LLR-BP) decoding algorithms and their reduced-complexity derivatives for low-density parity-check (LDPC) codes are presented. Numerically accurate representations of the check-node update computation used in LLR-BP decoding are described. Furthermore, approximate representations of the decoding computations are shown to achieve a reduction in complexity by simplifying the check-node update, or symbol-node update, or both. In particular, two main approaches for simplified check-node updates are presented that are based on the so-called min-sum approximation coupled with either a normalization term or an additive offset term. Density evolution is used to analyze the performance of these decoding algorithms, to determine the optimum values of the key parameters, and to evaluate finite quantization effects. Simulation results show that these reduced-complexity decoding algorithms for LDPC codes achieve a performance very close to that of the BP algorithm. The unified treatment of decoding techniques for LDPC codes presented here provides flexibility in selecting the appropriate scheme from performance, latency, computational-complexity, and memory-requirement perspectives. LEARNING OBJECTIVE: To understand about 2:4 Decoder in VHDL INPUT: Data / information about 2:4 Decoder OUTPUT : Simulated output of 2:4 Decoder in VHDL APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

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