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D FLIPFLOP

Platform : vlsi

IEEE Projects Years : 2002

This paper appears in: Electron Devices Meeting, 1991. IEDM '91. Technical Digest., International Date of Current Version: 06 August 2002 AIM : IMPLEMENTATION OF HIGH SPEED D FLIPFLOP ABSTRACT A D-flip flop IC and a 2:1 selector IC using DCFL have been developed for applications operating above 10 Gb/s. Memory cell type flip flop (MCFF) is used for the D-flip flop IC. These ICs are fabricated using 0.2 μm gate pseudomorphic inverted HEMTs (high electron mobility transistors), which show a high transconductance of 580 mS/mm, a high cutoff frequency of 110 GHz, and a low drain conductance of 17 mS/mm. The operations of the D-flip flop and the 2:1 selector ICs are confirmed up to 20 Gb/s by a measurement system composed of these ICs. The power dissipation is 430 mW for the D-flip flop IC and 170 mW for the 2:1 selector IC LEARNING OBJECTIVE: To understand about high speed D FLIPFLOP INPUT: Data / information about high speed D FLIPFLOP OUTPUT : Simulated output of high speed D-flip flop in VHDL APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

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