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BAUD RATE GENERATOR

Platform : vlsi

IEEE Projects Years : 2002

This paper appears in: Communications, IEEE Transactions on Issue Date: Apr 2002 AIM: IMPLEMENTATION OF LINEAR FEEDBACK SHIFT REGISTOR (LFSR) BASED BAUD RATE GENERATOR ABSTRACT This paper suggests the use of a prefilter before baud-rate timing recovery (Mueller and Muller 1976). It is shown that the timing phase of the baud-rate timing synchronizer can be set to a desirable timing phase, at which point a digital equalizer performs best, by proper prefiltering. The procedure for the optimal design of such a prefilter is developed under the assumption that the channel impulse response and desirable timing phase for equalization are known. Application of the proposed scheme to the gigabit Ethernet system demonstrated that prefiltering can improve receiver performance. LEARNING OBJECTIVE: To understand about linear feedback shift register (LFSR) based baud rate generator INPUT: Data / information about linear feedback shift registor (LFSR) based baud rate generator OUTPUT : Simulated output of linear feedback shift registor (LFSR) based baud rate generator APPLICATIONS: Very high speed integrated circuit hardware description language based design, VLSI Design SOSFTWARE TOOL USED: XLINX8.1I

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