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FIXED POINT UNIT (ALU)

Platform : vlsi

AIM: IMPLEMENTATION OF FIXED POINT UNIT (ALU) ABSTRACT Checking hardware products by building and then testing on a number of typical inputs and comparing the outputs with the expected results can be prohibitively expensive. So instead of designing practically, hardware design can be built using very high speed hardware description language. This paper will focus on the implementation of ALU design for multiplication based on Verilog hardware description language. In this case, the multiplier and multiplicand will be 32 bit unsigned integers. The syntax of Verilog HDL is similar to the C programming language. The purpose of using Verilog HDL is that it offers many features for hardware design. It allows easy and cheap debugging facilities for hardware. And by using Booth’s algorithm, multiplication can speed up. So this paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist. LEARNING OBJECTIVE: To understand about fixed point unit (ALU) INPUT: Data / information about fixed point unit (ALU) OUTPUT : Simulated output of fixed point unit (ALU) APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design SOSFTWARE TOOL USED: XLINX81I

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