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UNSIGNED SERIAL DIVIDER

Platform : vlsi

IEEE Projects Years : 1994

This paper appears in: Computers and Digital Techniques, IEE Proceedings. Issue Date: Nov 1994 AIM: IMPLEMENTATION OF DIGIT-SERIAL ARCHITECTURE FOR SERIAL DIVIDER ABSTRACT The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that it is based on the radix-2n algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The authors present two basic digit-serial controlled add/subtract cells. The first is based on the conventional carry feedback digit-serial adder. The second is based on the carry feed-forward adder, which results in the first reported digit-serial divider/square-root architecture that can be pipelined down to the bit-level. An evaluation of the proposed architecture for different values of the digit size is also presented LEARNING OBJECTIVE: To understand about Digit-serial architecture for serial divider INPUT: Data / information about Digit-serial architecture for serial divider OUTPUT : Simulated output of Digit-serial architecture for serial divider APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design SOSFTWARE TOOL USED: XLINX81I

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