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FPGA BASED POWER EFFICIENT CHANNELIZER FOR SOFTWARE DEFINED RADIO

Platform : vlsi

IEEE Projects Years : 2003

This paper appears in: Personal, Indoor and Mobile Radio Communications, 2003. PIMRC 2003. 14th IEEE Proceedings on Issue Date: 7-10 Sept. 2003 AIM: IMPLEMENTATION OF CHANNELIZER FOR SOFTWARE DEFINED RADIO ABSTRACT The flexibility of a software-defined radio (SRR) depends on its capability to operate in multi-standard wireless communication environments. The most computationally intensive part of wideband receivers is the channelizer, which extracts multiple narrowband signals from adjacent frequency hands. In an SDR receiver, the compatibility of the channelizer with different communication standards is guaranteed by its reconfigurability. This paper presents an efficient channelizer that has a reconfigurable architecture based on quadrature mirror filter bank (QMF) trees. We show that the channelizer can he efficiently implemented using common subexpression based filter structures. An example of dual-mode global system for mobile communication (GSM)/personal digital cellular (PDC) channelizer is discussed to illustrate the proposed design methodology. LEARNING OBJECTIVE: To understand about channelizer for software defined radio INPUT: Data / information about channelizer for software defined radio OUTPUT : Simulated output of channelizer for software defined radio APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design

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