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A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE

Platform : vlsi

IEEE Projects Years : 2007

This paper appears in: VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on Issue Date: Jan. 2007 AIM : IMPLEMENTATION OF UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER. ABSTRACT This paper describes a novel architecture of universal asynchronous receiver transmitter (UART) based on recursive running sum (RRS) filter. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The robust UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one third of required bit period. The intermediate data bit is decoded using magnitude comparator. A majority voter is used to decode actual data bit from three intermediate data bits. Comparison of MATLAB simulation results at different noise level shows that the robust UART described here has far better performance than standard UART at higher noise levels. Other advantage of this architecture is that baud rate is decided by the window size so there is no need of any external "timer module" which is normally required for standard UARTs. The robust UART core described here is designed using VHDL and implemented on Xilinx Virtex FPGA LEARNING OBJECTIVE: To understand operational issues of universal asynchronous receiver transmitter (UART) based on recursive running sum (RRS) filter INPUT: Data / information about universal asynchronous receiver transmitter (UART) OUTPUT : Simulated output of universal asynchronous receiver transmitter APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design SOFTWARE TOOL USED: XLINX81I

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