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MUTIPLIED ACCUMULATOR

Platform : vlsi

IEEE Projects Years : 2003

This paper appears in: Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International Issue Date: 2003 AIM:IMPLEMENTATION OF ACCUMULATOR ABSTRACT A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-VT CMOS process, the 2 mm2 prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25°C. LEARNING OBJECTIVE: To understand operational issues of Accumulator INPUT: Pool of Binary coded data (BCD) OUTPUT : Simulated output of Accumulated data based on given input APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design SOFTWARE TOOL USED: XLINX8.1I

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