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FIFO (ASYNC/SYNC)

Platform : vlsi

IEEE Projects Years : 2005

This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Issue Date: June 2005 AIM: IMPLEMENTATION OF ASYNCHRONOUS FIRST IN FIRST OUT (FIFO) ABSTRACT A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture. LEARNING OBJECTIVE: Operational issues of Asynchronous First In First Out (FIFO) INPUT: Data/ Information about 8-bit data OUTPUT : Simulated output of First In First Out of input data APPLICATIONS: Very high speed integrated circuit hardware description language design, VLSI Design SOFTWARE TOOL USED: XLINX8.1I

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