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CRC16/USB DATA APPLICATION

Platform : vlsi

IEEE Projects Years : 2004

This paper appears in: Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on Issue Date: 6-8 Dec. 2004 On page(s): 319 - 322 ISSN: Print ISBN: 0-7803-8651-5 INSPEC Accession Number: 8293048 Digital Object Identifier: 10.1109/FPT.2004.1393289 Date of Current Version: 14 February 2005 AIM: TO IMPLEMENTATION OF CYCLIC REDUDANCY CHECK 16 ABSTRACT Framing protocols employ cyclic redundancy check (CRC) to detect errors incurred during transmission. Generally whole frame is protected using CRC and upon detection of error, retransmission is requested. But certain protocols demand for single bit error correction capabilities for the header part of the frame, which often plays an important role in receiver synchronization. At a speed of 10 Gbps, header error correction implementation in hardware can be a bottleneck. This work presents a hardware efficient way of implementing CRC-16 over 16 bits of data, multiple bit error detection and single bit error correction on FPGA device. LEARNING OBJECTIVE: To understand about coding for cyclic redudancy check -16 INPUT: Information /data about cyclic redudancy check -16 OUTPUT : Simulated output for the CRC-16 APPLICATIONS: VLSI Design SOFTWARE TOOL USED: XLINX8.1I

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