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QPSK MODULATOR

Platform : vlsi

IEEE Projects Years : 1990

This paper appears in: Electronics Letters Issue Date: 5 July 1990 Volume: 26 Issue:14 On page(s): 961 - 962 ISSN: 0013-5194 References Cited: 2 INSPEC Accession Number: 3709646 Digital Object Identifier: 10.1049/el:19900625 Date of Current Version: 06 August 2002 Sponsored by: Institution of Engineering and Technology AIM: VHDL IMPLEMENTATION OF QPSK MODULATOR ABSTRACT A QPSK modulator with a 2.75-4.75 GHz operating frequency range is presented. The modulator is realised using a broadband power divider, microstrip-slotline-microstrip transitions and Lange couplers. Computer optimised matching circuits are used to maintain a phase error less than 5 degrees and an amplitude phase imbalance error across the band of less than 0.5 dB. The modulator is suitable for MMIC implementation. LEARNING OBJECTIVE: Thus the students are forced to learn the practical aspect of writing a synthesizable VHDL code and simulation of QPSK Modulator. INPUT: ASM machine for QPSK modulator OUTPUT : Simulated output for the QPSK Modulator. A synthesizable and efficient VHDL code. APPLICATIONS: Very high speed integrated circuit hardware description language design. VLSI Design SOFTWARE TOOL USED: XLINX8.1I

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