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FIFO TYPES

Platform : vlsi

IEEE Projects Years : 1994

This paper appears in: Test Conference, 1994. Proceedings., International Issue Date: 2-6 Oct1994 On page(s): 378 - 387 Meeting Date: 02 Oct 1994 - 06 Oct 1994 Location: Washington, DC , USA Print ISBN: 0-7803-2103-0 References Cited: 20 INSPEC Accession Number: 4847002 Digital Object Identifier: 10.1109/TEST.1994.527979 Date of Current Version: 06 August 2002 AIM: TO UNDERSTAND IMPLEMENTATION OF FIFO WITH THE RING-ADDRESS FIFO IS AN EXAMPLE ABSTRACT FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n2) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described LEARNING OBJECTIVE: Thus the students are forced to learn the practical aspect of writing a synthesizable VHDL code and simulation of the ring address FIFO. INPUT: Translating from a given algorithmic state machine (ASM) chart. e.g the ring address FIFO. OUTPUT : Simulated output for the ring address FIFO. A synthesizable and efficient VHDL code. APPLICATIONS: Very high speed integrated circuit hardware description language design. VLSI Design SOFTWARE TOOL USED: XLINX8.1I

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