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VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPT

Platform : vlsi

IEEE Projects Years : 2009

Abstract—A public competition organized by the NIST recently started, with the aim of identifying a new standard for cryptographic hashing (SHA-3). Besides a high security level, candidate algorithms should show good performance on various platforms. While an average performance on highend processors is generally not critical, implementability and exibility in hardware is crucial, because the new standard will be implemented in a variety of lightweight devices. This paper investigates VLSI architectures of the SHA-3 candidates MD6 and ïrRUPT. The fastest circuit is the 16parallel MD6 core, reaching 16.3 Gbps at a complexity of 69.8 k gate equivalents (GE) on ASIC and 8.4 Gbps using 4465 Slices on FPGA. However, large memory requirements preclude the application of MD6 to resource-constrained systems. The most exible and efcient circuit turns out to be our 2-ïrRUPT64x2-256/8 core, which achieves a throughput of 5.0 Gbps at 12.7 kGE on ASIC and 1.7 Gbps using 613 Slices on FPGA. I. INTRODUCTION

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